cache WB (Writeback) counter increment when reading cache line and D refill counter when writing into cache line #75
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SoCScholar
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SoCScholar
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Dolu1990
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Jan 15, 2024
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Hi, Should be fixed with that commit. not a bug in the L1, with coherency, the writeback path is also used to give back permissions, just had to include the dirty flag in the probe |
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Thank you, Do we also need to care of the inclusive part of the L2 cache to estimate the refill and writeback of L1 cache within Do we also need to change here? |
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Hi I tried with SBT of freshly clone git hub to see effect of recently change. I get following errors. have you check with SBT too ? i get HIERARCHY VIOLATION errors details of errors are below following is compilation problem in litex. errors are same |
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Ahh my bad, i forgot the pull. |
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Thank you < 3 Could it be possible to read the L2 cache WB (WriteBack) counter ? |
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you want to read a existing counter ? or create a new one ? Which counter exactly ? |
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Probably we need to create new one Below is just L2 cache miss or refill counter. Probably we need create a new counter to read the L2 cache WB (WriteBack) counter Which counter exactly: L2 cache WB (WriteBack) counter |
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Thank you < 3. Previously i was confuse whether it might be too tough to do it. now i tested in SBT server. it seems like it counting L2 cache WB (writeback) counter by 7 times more when i print the counter value when I perform reading of 1 MB memory size. |
Hooo that is right, have to add a check to only count up on the last beat of a burst : add(l2c.rework(l2c.io.down.a.fire && l2c.io.down.a.isLast() && l2c.io.down.a.opcode === spinal.lib.bus.tilelink.Opcode.A.PUT_FULL_DATA), 0xF30) |
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thank you so much <3 I will test it and will update you, |
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When i run in SBT, i can see value of the L2 cache write back counter being incremented but when run with litex framework in FPGA, value of L2 cache writeback doesnot increase at all. its just read 0. is there any issues while running in fpga I put the above code in NaxSoc.scala in following ways |
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Hi, How do you run your code in litex ? i mean, are you sure your code run in the DDR ? and not the on chip ram ? |
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Easy way to check it is to check its memory mapping. |
Yes I did double check and indeed my code is running in DDR. I am using arty a7 100t FPGA https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/ https://digilent.com/reference/programmable-logic/arty-a7/start |
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that is curious. |
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Yes in SBT simulation it woks perfectly ok but not in litex I first of all build/ compile and then load the bit stream into FPGA with litex provide build in bootloader that helps to download image over the serial connection. litex term command to download the binary file or my experimented code in such way this is the output |
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So, would need to look at the litex sim, to see if there is trafic or not on the l2 cache, to understand if the issue is on the probe side, or the setup side |
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How to do to see if there is traffic or not on the l2 cache ? i am kind of confuse now . I am working in litex sim since last week couldnot figure out where is the problem in litex sim as L2 WB counter works in SBT simulation properly. |
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By looking at the wave form generated by litex sim, via the args --trace --trace-fst if i remember well. |
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something like this below command to put |
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No, i mean that litex has some commands to run simulation. I 'm not talking about running stuff on FPGA |
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Hi charles i did as you suggested but still L2 cache WB counter read zero I tried following As you can see in this screenshot of litex sim
I tried to load
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Hi, You need both --trace and --trace-fst . Without --trace it will not add data to the fst file i think. Then should be good to vew with gtkwave |
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Hi again, I did so it gives such errors Am i doing it correctly ?? |
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You may need to install pyvcd : |
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Hi Charles,
when performing reading operations during the simulation and on FPGA,
SCOPE_HART_DCACHE_WRITEBACKcounter value is increased, which was not expected.#define SCOPE_HART_DCACHE_WRITEBACK(hart) ((hart) * 0x80 + 0x14) // Read only
I wonder why the WB counter is increased when reading the cache line.
Reading and writing test operation looks like this
Here each cache line is size of 64 bytes so we increase the pointer by 64 of char( 1 bytes). I try to read 64 bytes character that reflect each cache line size until 15 KB, 16 KB, and 1MB to see value of L1 D cache WB and L1 D cache refill counter.
as L1 cache size is of 16 KB and each cache line size is of 64 Byte, we try to experiment with a 15 KB, 16 KB, and 1MB test memory size.
Similarly,
when performing Write operations during the simulation and on FPGA,
SCOPE_HART_DCACHE_REFILLcounter value is increased, which was not expected.#define SCOPE_HART_DCACHE_REFILL(hart) ((hart) * 0x80 + 0x10) // Read only
I also wonder why the
DCACHE_REFILLcounter is increased when Writing into the cache line.is there might be a bug in Spinal HDL while designing the NAX L1 cache architecture?
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