Spv merge to spv 7

mflowgen/bin/setup-buildkite.sh

@@ -458,7 +458,10 @@ else
       if [ -d adks/gf12-adk ]; then
           cd adks/gf12-adk; git pull
       elif [ -d adks/tsmc16-adk ]; then
-          cd adks/tsmc16-adk; git pull
+          cd adks/tsmc16-adk; git pull || (\
+              echo "+++ WARNING: Could not 'git pull' to retrieve latest version of tsmc16-adk";
+              echo "=> see mflowgen/bin/setup-buildkite.sh"; echo "."; echo "."
+          )
       else
           echo "ERROR ADK not found"
           return 13 || exit 13

mflowgen/common/custom-power-chip/outputs/globalnetconnect.tcl

@@ -1,15 +1,38 @@
+set WHICH_SOC "onyx"
+if { [info exists ::env(WHICH_SOC)] } { set WHICH_SOC $::env(WHICH_SOC) }
+
 # Same as everyone else
 globalNetConnect VDD -type pgpin -pin VDD -inst *
 globalNetConnect VDD -type tiehi
 globalNetConnect VSS -type pgpin -pin VSS -inst *
 globalNetConnect VSS -type tielo
+if { $WHICH_SOC == "amber" } {
+globalNetConnect VDD -type pgpin -pin VPP -inst *
+globalNetConnect VSS -type pgpin -pin VBB -inst *
+} else {
 globalNetConnect VSS -type pgpin -pin VPW -inst *
 globalNetConnect VDD -type pgpin -pin VNW -inst *
+}
 
+if { $WHICH_SOC == "amber" } {
+# I/O power nets
+globalNetConnect VDDPST -type pgpin -pin VDDPST -inst *
+globalNetConnect VSS    -type pgpin -pin VSSPST -inst * 
+} else {
 # I/O pads
 globalNetConnect VDDPST -type pgpin -pin VDDIO -inst *
 globalNetConnect VSS    -type pgpin -pin VSSIO -inst * 
 globalNetConnect VSS    -type pgpin -pin VSSC -inst * 
 globalNetConnect VSS    -type pgpin -pin VSS_CM -inst * 
 globalNetConnect VDD    -type pgpin -pin VDDC -inst * 
+}
 
+if { $WHICH_SOC == "amber" } {
+# Dragonphy power nets
+globalNetConnect VDD -type pgpin -pin DVDD -inst iphy -override
+globalNetConnect VSS -type pgpin -pin DVSS -inst iphy -override
+globalNetConnect AVDD -type pgpin -pin AVDD -inst iphy -override
+globalNetConnect AVSS -type pgpin -pin AVSS -inst iphy -override
+globalNetConnect CVDD -type pgpin -pin CVDD -inst iphy -override
+globalNetConnect CVSS -type pgpin -pin CVSS -inst iphy -override
+}

mflowgen/common/power-domains/outputs/pd-globalnetconnect.tcl

@@ -1,4 +1,5 @@
-
+set WHICH_SOC "onyx"
+if { [info exists ::env(WHICH_SOC)] } { set WHICH_SOC $::env(WHICH_SOC) }
 
 #-------------------------------------------------------------------------
 # Global net connections for PG pins
@@ -11,7 +12,12 @@
 globalNetConnect VDD_SW -type tiehi -powerdomain TOP
 globalNetConnect VDD    -type tiehi -powerdomain AON
 globalNetConnect VSS    -type tielo
-globalNetConnect VDD    -type pgpin -pin VNW -inst *
-globalNetConnect VSS    -type pgpin -pin VPW -inst *
-globalNetConnect VDD    -type pgpin -pin VDDC -inst *
-
+if { $WHICH_SOC == "amber" } {
+    globalNetConnect VDD    -type pgpin -pin VPP -inst *
+    globalNetConnect VSS    -type pgpin -pin VBB -inst *
+    globalNetConnect VDD    -type pgpin -pin TVDD -inst *HDR*
+} else {
+    globalNetConnect VDD    -type pgpin -pin VNW -inst *
+    globalNetConnect VSS    -type pgpin -pin VPW -inst *
+    globalNetConnect VDD    -type pgpin -pin VDDC -inst *
+}

mflowgen/common/power-scripts/globalnetconnect.tcl

@@ -8,12 +8,20 @@
 # Global net connections for PG pins
 #-------------------------------------------------------------------------
 
+set WHICH_SOC "onyx"
+if { [info exists ::env(WHICH_SOC)] } { set WHICH_SOC $::env(WHICH_SOC) }
+
 # Connect VNW / VPW if any cells have these pins
 
 globalNetConnect VDD -type pgpin -pin VDD -inst *
 globalNetConnect VDD -type tiehi
 globalNetConnect VSS -type pgpin -pin VSS -inst *
 globalNetConnect VSS -type tielo
-globalNetConnect VSS -type pgpin -pin VPW -inst *
-globalNetConnect VDD -type pgpin -pin VNW -inst *
 
+if { $WHICH_SOC == "amber" } {
+    globalNetConnect VDD -type pgpin -pin VPP -inst *
+    globalNetConnect VSS -type pgpin -pin VBB -inst *
+} else {
+    globalNetConnect VSS -type pgpin -pin VPW -inst *
+    globalNetConnect VDD -type pgpin -pin VNW -inst *
+}

mflowgen/common/soc-rtl-v2/rtl-scripts-amber/nic400_include_paths.tcl

@@ -0,0 +1,30 @@
+# ==============================================================================
+# Include Paths for NIC400 IP
+# ==============================================================================
+
+set soc_inc_nic400 [concat \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_CGRA_DATA/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_CGRA_REG/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_PERIPH/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_SRAM0/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_SRAM1/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_SRAM2/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_SRAM3/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_TLX/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/amib_master_TLX_REG/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/asib_slave_CPU/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/asib_slave_DMA0/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/asib_slave_DMA1/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/busmatrix_bm0/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/cdc_blocks/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/default_slave_ds_1/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_master_CGRA_DATA_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_master_CGRA_REG_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_master_PERIPH_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_master_TLX_REG_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_master_TLX_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/ib_slave_CPU_ib/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/reg_slice/verilog \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/nic400/verilog/Axi \
+  inputs/rtl/aham3soc_armip/logical/nic400_AhaIntegration/nic400/verilog/Ahb \
+]

mflowgen/common/soc-rtl-v2/rtl-scripts-amber/soc_design_files.tcl

@@ -0,0 +1,87 @@
+# ==============================================================================
+# loads SOC design files (RTL)
+# ==============================================================================
+# Cortex-M3 Files
+set soc_cm3_files [concat [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_wic/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_itm/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_tpiu/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_fpb/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_mpu/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_dwt/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_nvic/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_dpu/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_dap_ahb_ap/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cm3_bus_matrix/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/dapswjdp/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cortexm3/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/cortexm3_integration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cortex-m3/models/cells -types f *.v ] ]
+
+# CMSDK Files
+set soc_cmdk_files [concat [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_apb_uart/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_apb_watchdog/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_ahb_to_apb/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_apb_timer/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_ahb_to_sram/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/cmsdk/cmsdk_ahb_eg_slave/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/AhaPeriphAhbMtx/verilog/AhaPeriphAhbMtx -types f *.v ] ]
+
+# AXI SRAM Interface Converter
+set soc_sram_if_files [ glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/if_converters/axi_sram_if -types f *.v]
+
+# Integration Files
+set soc_integration_files [concat [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaCM3CodeRegionIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaCM3Integration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaDmaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaGarnetIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaGarnetSoC/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaMemIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaPeripherals/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaPlatformController/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaPlatformController/rdl/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaSoCPartialIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaTlxIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaTlxIntegration/rdl/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc/hardware/logical/AhaStdCells/asic/verilog -types f *.v]]
+
+# PL330 DMA Files
+set soc_dma_files [concat [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_dma_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_axi_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_icache_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_lsq_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_pipeline_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_mfifo_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_engine_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_merge_buffer_AhaIntegration/verilog -types f *.v] [
+  glob -nocomplain -directory inputs/rtl/aham3soc_armip/logical/DMA330_AhaIntegration/logical/pl330_dma_AhaIntegration/pl330_periph_AhaIntegration/verilog -types f *.v]]
+
+# TLX-400 Files
+source inputs/rtl-scripts/tlx_design_files.tcl
+
+# NIC-400 Files
+source inputs/rtl-scripts/nic400_design_files.tcl
+
+# All SoC Files
+set soc_design_files [concat \
+  $soc_cm3_files \
+  $soc_cmdk_files \
+  $soc_sram_if_files \
+  $soc_integration_files \
+  $soc_dma_files \
+  $soc_tlx_files \
+]
+
+
+set soc_design_files [concat \
+  $soc_cm3_files \
+  $soc_cmdk_files \
+  $soc_sram_if_files \
+  $soc_integration_files \
+  $soc_dma_files \
+  $soc_tlx_files \
+  $soc_nic400_files \
+]

mflowgen/full_chip/constraints_amber/configure.yml

@@ -0,0 +1,26 @@
+#=========================================================================
+# Constraints
+#=========================================================================
+# Author : Alex Carsello
+# Date   : Nov 1, 2019
+#
+# Edited by
+# Gedeon Nyengele
+# May 14, 2020
+#-------------------------------------------------------------------------
+
+name: constraints
+
+#-------------------------------------------------------------------------
+# Outputs
+#-------------------------------------------------------------------------
+outputs:
+  - constraints.tcl
+  - cons_scripts
+
+#-------------------------------------------------------------------------
+# Commands
+#-------------------------------------------------------------------------
+commands:
+- cp -L cons_scripts/constraints.tcl outputs
+- cp -RL cons_scripts outputs

mflowgen/full_chip/constraints_amber/cons_scripts/clocks_0_params.tcl

@@ -0,0 +1,23 @@
+#-----------------------------------------------------------------------------
+# TCL Script
+#-----------------------------------------------------------------------------
+# Purpose: Clock Parameters
+#------------------------------------------------------------------------------
+#
+# Author   : Gedeon Nyengele
+# Date     : May 17, 2020
+#------------------------------------------------------------------------------
+
+# ------------------------------------------------------------------------------
+# Clock Period
+# ------------------------------------------------------------------------------
+
+set cgra_master_clk_period          ${clock_period}
+set soc_master_clk_period           1.0
+
+# ------------------------------------------------------------------------------
+# Clock Division Factors
+# ------------------------------------------------------------------------------
+
+set cgra_clk_div_factor             1
+set soc_clk_div_factor              2

mflowgen/full_chip/constraints_amber/cons_scripts/clocks_1_master.tcl

@@ -0,0 +1,58 @@
+#-----------------------------------------------------------------------------
+# TCL Script
+#-----------------------------------------------------------------------------
+# Purpose: Create Master Clocks
+#------------------------------------------------------------------------------
+#
+# Author   : Gedeon Nyengele
+# Date     : May 17, 2020
+#------------------------------------------------------------------------------
+
+# ------------------------------------------------------------------------------
+# Create Master Clocks
+# ------------------------------------------------------------------------------
+
+create_clock -name master_clk_0 -period ${cgra_master_clk_period} [get_ports $port_names(master_clk)]
+
+create_clock -name master_clk_1 -period ${soc_master_clk_period} [get_pins core/ALT_MASTER_CLK]
+
+# ------------------------------------------------------------------------------
+# Muxed Master Clocks
+# ------------------------------------------------------------------------------
+
+create_generated_clock -name m_clk_0 \
+    -source [get_ports $port_names(master_clk)] \
+    -divide_by 1 \
+    [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_master_clock_switch/CLK_OUT]
+
+create_generated_clock -name m_clk_1 \
+    -source [get_pins core/ALT_MASTER_CLK] \
+    -divide_by 1 \
+    -add \
+    -master_clock master_clk_1 \
+    [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_master_clock_switch/CLK_OUT]
+
+
+# ------------------------------------------------------------------------------
+# Create Divided Clocks
+# ------------------------------------------------------------------------------
+
+set clk_div_factors   [list 1 2 4 8 16 32]
+
+foreach idx $clk_div_factors {
+  # From Master 0
+  create_generated_clock -name by_${idx}_mst_0_clk \
+      -source [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_master_clock_switch/CLK_OUT] \
+      -divide_by ${idx} \
+      -master_clock m_clk_0 \
+      -add \
+      [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_clk_div/CLK_by_${idx}]
+
+  # From Master 1
+  create_generated_clock -name by_${idx}_mst_1_clk \
+      -source [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_master_clock_switch/CLK_OUT] \
+      -divide_by ${idx} \
+      -master_clock m_clk_1 \
+      -add \
+      [get_pins core/u_aha_platform_ctrl/u_clock_controller/u_clk_div/CLK_by_${idx}]
+}