add new predictor(acc ~95%)

source/sources_1/new/defines/defines.svh

@@ -265,6 +265,41 @@ typedef logic [5:0] ARFNum; // 逻辑寄存器编号(共34个)
 `define NOP_U       8'b01000010
 `define WAIT_U      8'b01000101
 
+// BranchPred
+`define GHLEN 20
+`define BHRLEN 4
+`define PHTIDXLEN_G 10 
+typedef logic [`GHLEN-1:0] GlobalHist;           // Index used for indexing BHR Table
+typedef logic [1:0] PHTEntry;           // One entry in PHT Table
+typedef logic [`PHTIDXLEN_G-1:0] PHTIndex_G;           // PHT Index
+typedef struct packed {
+    PHTIndex_G pht_index_g;
+} GlobalHistPred;
+
+`define BHTIDXLEN 8
+`define BHRLEN 4
+`define PHTIDXLEN 10 
+`define CPHT_ENTRY 1024
+typedef logic [`BHTIDXLEN-1:0] BHTIndex;           // Index used for indexing BHR Table
+typedef logic [`BHRLEN-1:0] BHREntry;           // One entry in BHR Table
+typedef logic [`PHTIDXLEN-1:0] PHTIndex;           // PHT Index
+typedef logic [9:0] CPHTIndex;
+typedef logic [1:0] CPHT_Entry;
+typedef struct packed {
+    BHTIndex bht_index;
+    PHTIndex pht_index;
+} LocalHistPred;
+
+typedef struct packed {
+    BHTIndex bht_index;
+    PHTIndex pht_index;
+    PHTIndex_G pht_index_g;
+    CPHTIndex cpht_index;
+    logic use_global;
+} PredInfo;
+
+
+
 typedef logic [9:0] TAGEIndex;
 typedef logic [2:0] TAGECtr;
 typedef logic [7:0] TAGETag;
@@ -291,7 +326,7 @@ typedef struct packed {
     logic           isJ;
     logic           valid;
     NLPPredInfo     nlpInfo;
-    TAGEPred        bpdInfo;
+    PredInfo        bpdInfo;
     logic           predTaken;
     logic   [31:0]  predAddr;
     logic           jBadAddr;
@@ -541,7 +576,7 @@ typedef struct packed {
 
     logic                   predTaken;
     logic   [31:0]          predAddr;
-    TAGEPred                predInfo;
+    PredInfo                predInfo;
     logic   [1:0]           nlpBimState;
 
     logic                   causeExc;

source/sources_1/new/ifu/CtrlUnit.sv

@@ -14,11 +14,11 @@ module CtrlUnit(
     Ctrl.master     ctrl_tage
 );
 
-    logic delayIF3Flush, if3Flush;
+    logic delayIF3Flush, if3Flush, delayedbkdFlush;
 
     always_ff @ (posedge clk) delayIF3Flush <= ctrl_if3.flushReq;
     assign if3Flush = delayIF3Flush || ctrl_if3.flushReq;
-
+    always_ff @(posedge clk) delayedbkdFlush <= backend_ctrl.flush;
 
     assign ctrl_if0_1_regs.pause        = ctrl_instBuffer.pauseReq || ctrl_iCache.pauseReq;
     assign ctrl_if2_3_regs.pause        = ctrl_instBuffer.pauseReq;
@@ -29,7 +29,7 @@ module CtrlUnit(
 
     assign ctrl_if0_1_regs.flush        = `FALSE; //backend_ctrl.flush || ctrl_if3.flushReq;
     assign ctrl_iCache.flush            = backend_ctrl.flush || ctrl_if3.flushReq;
-    assign ctrl_tage.flush              = backend_ctrl.flush;
+    assign ctrl_tage.flush              = delayedbkdFlush;
     assign ctrl_if2_3_regs.flush        = backend_ctrl.flush || ctrl_if3.flushReq;
     assign ctrl_if3.flush               = backend_ctrl.flush;
     assign ctrl_if3_output_regs.flush   = backend_ctrl.flush;

source/sources_1/new/ifu/IFU.sv

@@ -51,26 +51,45 @@ module IFU(
     logic IF3_isBranch, IF3_isJ;
     wire [31:0] pred_target;
     wire pred_valid, pred_taken;
-    TAGEPred pred_info;
-    TAGE u_TAGE(
+    assign pred_valid = 1;
+    // TAGEPred pred_info;
+    // TAGE u_TAGE(
+    //     .clk                    (clk                    ),
+    //     .rst                    (rst                    ),
+    //     .pause                  (ctrl_tage.pause        ),
+    //     .recover                (ctrl_tage.flush        ),
+    //     .IF3_isBranch           (IF3_isBranch           ),
+    //     .IF3_isJ                (IF3_isJ                ),
+    //     .br_pc                  (regs_iCache.PC         ),
+    //     // 送出的结果
+    //     .pred_valid             (pred_valid             ),
+    //     .pred_taken             (pred_taken             ),
+    //     .pred_target            (pred_target            ),
+    //     .pred_info              (pred_info              ),
+    //     // 从commit阶段来的
+    //     .commit_valid           (backend_bpd.updValid   ),
+    //     .committed_target       (backend_bpd.updTarget  ),
+    //     .committed_pred_info    (backend_bpd.updInfo    ),
+    //     .committed_branch_taken (backend_bpd.updTaken   ),
+    //     .committed_mispred      (backend_bpd.updMisPred )
+    // );
+    PredInfo pred_info;
+    assign pred_target = 0;
+    Predictor bpd_u(
         .clk                    (clk                    ),
         .rst                    (rst                    ),
-        .pause                  (ctrl_tage.pause        ),
+        // .pause                  (ctrl_tage.pause        ),
+    // 注意：此处的recover接的是regfile的recover，需要等分支指令提交进来了再进行恢复
         .recover                (ctrl_tage.flush        ),
-        .IF3_isBranch           (IF3_isBranch           ),
+        .IF3_isBR               (IF3_isBranch           ),
         .IF3_isJ                (IF3_isJ                ),
-        .br_pc                  (regs_iCache.PC         ),
-        // 送出的结果
-        .pred_valid             (pred_valid             ),
-        .pred_taken             (pred_taken             ),
-        .pred_target            (pred_target            ),
+        .br_PC                  (regs_iCache.PC         ),
         .pred_info              (pred_info              ),
-        // 从commit阶段来的
+        .pred_taken             (pred_taken             ),
         .commit_valid           (backend_bpd.updValid   ),
         .committed_target       (backend_bpd.updTarget  ),
         .committed_pred_info    (backend_bpd.updInfo    ),
         .committed_branch_taken (backend_bpd.updTaken   ),
         .committed_mispred      (backend_bpd.updMisPred )
-    );
-
+);  
 endmodule

source/sources_1/new/ifu/branch_predict.sv

@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+`include "../defines/defines.svh"
+module Predictor(
+    input clk,
+    input rst,
+    // 注意：此处的recover接的是regfile的recover，需要等分支指令提交进来了再进行恢复
+    input recover,
+    input [31:0] br_PC,
+    input IF3_isBR,
+    input IF3_isJ,
+    output PredInfo pred_info,
+    output reg pred_taken,
+    input commit_valid,
+    input PredInfo committed_pred_info,
+    input [31:0] committed_target,
+    input committed_branch_taken,
+    input committed_mispred
+);  
+    // 虽然是竞争的分支预测，也需要对两个进行更新
+    // 两个具有一周期延时的预测器
+    GlobalHistPred pred_info_global_o;
+    LocalHistPred pred_info_local_o;
+    BHREntry bhr;
+    GlobalHist ghist;
+    wire pred_taken_global, pred_taken_local;
+    CPHTIndex CPHT_index, CPHT_index_update;
+    CPHT_Entry [1023:0] CPHT;
+    wire [31:0] br_PC_dly;
+    // 内部拥有1级的pipeline
+    LocalHistPred committed_pred_info_local;
+    assign committed_pred_info_local.bht_index = committed_pred_info.bht_index;
+    assign committed_pred_info_local.pht_index = committed_pred_info.pht_index;
+    LocalHistPredictor localhist(
+        .clk(clk),
+        .rst(rst),
+        .br_PC(br_PC),
+        .pred_info(pred_info_local_o),
+        .bhr(bhr),
+        .pred_taken(pred_taken_local),
+        .commit_update(commit_valid),
+        .committed_pred_info(committed_pred_info_local),
+        .committed_taken(committed_branch_taken),
+        .br_PC_out(br_PC_dly)
+    );
+
+    GlobalHistPred committed_pred_info_global;
+    assign committed_pred_info_global.pht_index_g = committed_pred_info.pht_index_g;
+    GlobalHistPredictor globalhist(
+        .clk(clk),
+        .rst(rst),
+        .br_PC(br_PC),
+        .recover(recover),
+        .pred_info(pred_info_global_o),
+        .ghist(ghist),
+        .pred_taken(pred_taken_global),
+        // For updating global histroy
+        .pred_valid_local(IF3_isBR || IF3_isJ),    // ToDo
+        .pred_taken_local(pred_taken || IF3_isJ),
+        .commit_update(commit_valid),
+        .committed_pred_info(committed_pred_info_global),
+        .committed_taken(committed_branch_taken)
+    );
+
+
+    // Stage 2: Take the output and select the working predictor
+
+    assign CPHT_index_update = committed_pred_info.cpht_index ;
+    assign CPHT_index= ghist[19:10] ^ ghist[9:0] ^ br_PC_dly[12:3];
+
+    always @(posedge clk)   begin
+        if(rst) begin
+            for(integer i = 0; i < 1024; i++)   begin
+                CPHT[i] <= 0;
+            end
+        end else if(commit_valid) begin
+            // TODO
+            if(committed_pred_info.use_global && committed_mispred)   begin
+                CPHT[CPHT_index_update] <= CPHT[CPHT_index_update] == 2'b00 ? 2'b00 : CPHT[CPHT_index_update] - 2'b01;
+            end else begin
+                CPHT[CPHT_index_update] <= CPHT[CPHT_index_update] == 2'b11 ? 2'b11 : CPHT[CPHT_index_update] + 2'b01;
+            end
+        end
+    end
+
+    wire pred_taken_o, use_global_o;
+    assign pred_taken_o = CPHT[CPHT_index] == 1 ? pred_taken_global : pred_taken_local;
+    assign use_global_o = CPHT[CPHT_index] == 1;
+
+    // Output logic
+    PredInfo pred_info_o;
+    assign pred_info_o.bht_index = pred_info_local_o.bht_index;
+    assign pred_info_o.pht_index = pred_info_local_o.pht_index;
+    assign pred_info_o.pht_index_g = pred_info_global_o.pht_index_g;
+    assign pred_info_o.cpht_index = CPHT_index;
+    assign pred_info_o.use_global = use_global_o;
+    always @(posedge clk)   begin
+        if(rst) begin
+            pred_info <= 0;
+            pred_taken <= 0;
+        end else begin
+            pred_info <= pred_info_o;
+            pred_taken <= pred_taken_o;
+        end
+    end
+
+
+
+endmodule

source/sources_1/new/ifu/global_hist.sv

@@ -0,0 +1,77 @@
+`timescale 1ns / 1ps
+`include "../defines/defines.svh"
+
+module GlobalHistPredictor(
+    input clk,
+    input rst,
+    input recover,
+    input [31:0] br_PC,
+    output GlobalHistPred pred_info,
+    output GlobalHist ghist,
+    output pred_taken,
+    input pred_valid_local,
+    input pred_taken_local,
+    input commit_update,
+    input GlobalHistPred committed_pred_info,
+    input committed_taken
+);
+    // 2 Pipeline stage
+    // 1 Cycle Delay
+    // Output is not registered
+    GlobalHist ghist_committed;
+
+    PHTEntry [1023:0] PHT;
+    PHTEntry current_ph;
+    PHTIndex_G pht_index, pht_index_r;
+    assign pht_index = ghist[19:10] ^ ghist[9:0] ^ br_PC[12:3]; // TODO
+
+    // Pipeline Register
+    always @(posedge clk)   begin
+        if(rst) begin
+            pht_index_r <= 0;
+        end else begin
+            pht_index_r <= pht_index;
+        end
+    end
+
+    assign current_ph = PHT[pht_index_r];
+    assign pred_taken = current_ph[1];
+    assign pred_info.pht_index_g = pht_index_r;
+
+
+    PHTEntry pht_inc;
+    PHTEntry pht_dec;
+
+    assign pht_inc = PHT[committed_pred_info.pht_index_g] == 2'b11 ? 2'b11 : PHT[committed_pred_info.pht_index_g] + 2'b01;
+    assign pht_dec = PHT[committed_pred_info.pht_index_g] == 2'b00 ? 2'b00 : PHT[committed_pred_info.pht_index_g] - 2'b01;
+
+    // Update of global history(speculatively)
+    always @(posedge clk)   begin
+        if(rst) begin
+            ghist <= 0;
+        end else if(recover) begin
+            ghist <= ghist_committed;
+        end else if(pred_valid_local) begin
+            ghist <= { ghist[`GHLEN-2:0], pred_taken_local };
+        end
+    end
+    // Update the committed global history
+    always @(posedge clk)   begin
+        if(rst) begin
+            ghist_committed <= 0;
+        end else if(commit_update) begin
+            ghist_committed <= { ghist_committed[`GHLEN-2:0], committed_taken };
+        end
+    end
+    // Update logic
+    always @(posedge clk)   begin
+        if(rst) begin
+            for(integer i=0;i<1024;i++) begin
+                PHT[i] <= 0;
+            end
+        end else if(commit_update) begin
+            PHT[committed_pred_info.pht_index_g] <= committed_taken ? pht_inc : pht_dec;
+        end
+    end
+
+endmodule