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genvar declaration should start its own line/partition #151

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fangism opened this issue Jan 24, 2020 · 2 comments
Closed

genvar declaration should start its own line/partition #151

fangism opened this issue Jan 24, 2020 · 2 comments
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formatter Verilog code formatter issues good first issue Good for newcomers

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@fangism
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fangism commented Jan 24, 2020

Input:

always_comb begin end
genvar i;
generate
for (i = 0; i < 4; i++) begin end
endgenerate

bad output:

always_comb begin
end genvar i;
generate
  for (i = 0; i < 4; i++) begin
  end
endgenerate

genvar i; should start its own partition/line.

@fangism fangism added the formatter Verilog code formatter issues label Jan 24, 2020
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fangism commented Jan 24, 2020

b/148296781

@fangism fangism added the good first issue Good for newcomers label Jan 24, 2020
@fangism
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fangism commented Jan 24, 2020

@rkapuscik rkapuscik self-assigned this Feb 4, 2020
@hzeller hzeller closed this as completed in 2b217b6 Feb 5, 2020
nikhiljha pushed a commit to nikhiljha/verible that referenced this issue Sep 27, 2022
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Labels
formatter Verilog code formatter issues good first issue Good for newcomers
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