Skip to content

Issues: chipsalliance/verible

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

Migrate name style rules to regex enhancement New feature or request style-linter Verilog style-linter issues
#2074 opened Jan 13, 2024 by IEncinas10
10 tasks
Enhance SyntaxTreeRule testing by pointing to syntax errors when present enhancement New feature or request style-linter Verilog style-linter issues testing matters pertaining to unit-tests, integration-tests, continuous/presubmit testing
#2007 opened Aug 30, 2023 by IEncinas10
Documentation: show how to create a compilation database with bazel documentation Improvements or additions to documentation
#1996 opened Aug 10, 2023 by IEncinas10
ProTip! Adding no:label will show everything without a label.