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GR716: Implement plo copy to SRAM #252

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Jun 22, 2023
Merged

GR716: Implement plo copy to SRAM #252

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c8dec61
sparcv8leon3: implement plo copy to SRAM
lukileczo May 4, 2023
20f205b
add AREA_KERNEL for kernel data in SRAM
lukileczo May 5, 2023
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113 changes: 109 additions & 4 deletions hal/sparcv8leon3/_init.S
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Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,118 @@
#include "config.h"
#include "../cpu.h"

.extern _plo_load_addr
.extern _plo_size

.section ".init", "ax"
.align 4
.global _init
.type _init, #function
_init:
/* get current PC */
call . + 8
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nop
mov %o7, %g5
/* check where we're loaded */
set _plo_load_addr, %g2
cmp %g5, %g2
bge stage1

/* Enable CGU for SRAM */
set 0x80006000, %g1 /* %g1 = cgu_unlock */
add %g1, 0x8, %g3 /* %g3 = cgu_core_reset */
add %g1, 0x4, %g4 /* %g4 = cgu_clk_en */
ld [%g1], %g2
or %g2, 0x10, %g2
st %g2, [%g1]

ld [%g3], %g2
or %g2, 0x10, %g2
st %g2, [%g3]

ld [%g4], %g2
or %g2, 0x10, %g2
st %g2, [%g4]

ld [%g4], %g2
andn %g2, 0x10, %g2
st %g2, [%g4]

ld [%g3], %g2
andn %g2, 0x10, %g2
st %g2, [%g3]

ld [%g4], %g2
or %g2, 0x10, %g2
st %g2, [%g4]

ld [%g1], %g2
andn %g2, 0x10, %g2
st %g2, [%g1]

/* Initialize SRAM pins */
sethi %hi(0x8030C000), %g1
sethi %hi(0xFE1FFFFF), %g3
or %g3, %lo(0xFE1FFFFF), %g3
st %g3, [%g1]

sethi %hi(0x8030D000), %g1
sethi %hi(0x1E0000), %g3
or %g3, 7, %g3
st %g3, [%g1]

sethi %hi(0x8000D000), %g1
sethi %hi(0x22222000), %g2
or %g2, 0x222, %g4
st %g4, [%g1]

/* 0x8000D004 */
add %g1, 0x4, %g1
st %g4, [%g1]

/* 0x8000D008 */
add %g1, 0x4, %g1
set 0x22222, %g3
st %g3, [%g1]

/* 0x8000D00C */
add %g1, 0x4, %g1
or %g2, %lo(0x22222220), %g3
st %g3, [%g1]

/* 0x8000D010 */
add %g1, 0x4, %g1
mov 0x222, %g3
st %g3, [%g1]

/* 0x8000D018 */
add %g1, 0x8, %g1
set 0x22220, %g3
st %g3, [%g1]

/* Set SRAM bank size and enable bus ready signalling */
set 0x80000004, %g1
set ((0xF << 9) | (1 << 7)), %g2
st %g2, [%g1]

/* Copy plo to SRAM */
set _plo_size, %g1
/* src = %g5 - 0x1000 */
set 0x1000, %g3
sub %g5, %g3, %g2 /* src */
set _plo_load_addr, %g3 /* dst */
add %g3, %g1, %g4 /* end */

copy:
ld [%g2], %g5
add %g2, 4, %g2
st %g5, [%g3]
add %g3, 4, %g3
cmp %g3, %g4
bl copy
nop

stage1:
/* Set up trap table */
sethi %hi(_trap_table), %g1
wr %g1, %tbr
Expand All @@ -39,9 +146,7 @@ _init:
mov %psr, %g1
or %g1, (PSR_ET | PSR_S), %g1
wr %g1, %psr
nop
nop
nop

call _startc
sethi %hi(_startc), %g1
jmpl %g1 + %lo(_startc), %g0
mov %g0, %g1
4 changes: 2 additions & 2 deletions hal/sparcv8leon3/_traps.S
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Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@

#define RESET \
mov %g0, %g4; \
sethi %hi(_init), %g4; \
jmp %g4 + %lo(_init); \
call _init; \
nop; \
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nop;


Expand Down
38 changes: 0 additions & 38 deletions hal/sparcv8leon3/gr716/gr716.c
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Expand Up @@ -138,43 +138,6 @@ static void _gr716_pllSetDefault(void)
}


/* Initialize external SRAM */
static void _gr716_sram_init(void)
{
io_cfg_t ioCfg;

_gr716_cguClkEnable(cgu_primary, cgudev_ftmctrl);
/* Set up addr pins */
for (size_t i = 0; i <= 20; i++) {
ioCfg.pin = i;
ioCfg.dir = 1;
ioCfg.opt = 2;
ioCfg.pullup = 0;
ioCfg.pulldn = 0;
_gr716_ioCfg(&ioCfg);
}
/* Set up data pins */
for (size_t i = 25; i <= 34; i++) {
ioCfg.pin = i;
ioCfg.dir = 1;
ioCfg.opt = 2;
ioCfg.pullup = 0;
ioCfg.pulldn = 0;
_gr716_ioCfg(&ioCfg);
}
for (size_t i = 49; i <= 52; i++) {
ioCfg.pin = i;
ioCfg.dir = 1;
ioCfg.opt = 2;
ioCfg.pullup = 0;
ioCfg.pulldn = 0;
_gr716_ioCfg(&ioCfg);
}
/* Set SRAM bank size and enable bus ready signalling */
*(gr716_common.mctrl0_base + mctrl_cfg2) |= (0xf << 9) | (1 << 7);
}


/* Enable (1) / disable (0) interrupts from PLL and clock logic */
void _gr716_pllIntCfg(u8 en)
{
Expand Down Expand Up @@ -259,5 +222,4 @@ void _gr716_init(void)
gr716_common.mctrl0_base = MCTRL0_BASE;

_gr716_pllSetDefault();
_gr716_sram_init();
}
16 changes: 8 additions & 8 deletions ld/sparcv8leon3-gr716.ldt
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
#define SIZE_PAGE 0x200
#define SIZE_STACK (8 * SIZE_PAGE)
#define SIZE_HEAP (8 * SIZE_PAGE)

#define AREA_KERNEL 0x100000

#if defined(__LINKER__)

Expand All @@ -17,15 +17,15 @@ MEMORY
m_spi1 : ORIGIN = 0x04000000, LENGTH = 32M
m_dram : ORIGIN = 0x30000000, LENGTH = 64K
m_iocram : ORIGIN = 0x31000000, LENGTH = 128K
m_sram : ORIGIN = 0x40000000, LENGTH = 2M
m_sram : ORIGIN = 0x40000000 + AREA_KERNEL, LENGTH = 2M - AREA_KERNEL
}

REGION_ALIAS("PLO_IMAGE", m_iocram)
REGION_ALIAS("RODATA", m_dram)
REGION_ALIAS("DATA", m_dram)
REGION_ALIAS("BSS", m_dram)
REGION_ALIAS("HEAP", m_dram)
REGION_ALIAS("STACK", m_dram)
REGION_ALIAS("PLO_IMAGE", m_sram)
REGION_ALIAS("RODATA", m_sram)
REGION_ALIAS("DATA", m_sram)
REGION_ALIAS("BSS", m_sram)
REGION_ALIAS("HEAP", m_sram)
REGION_ALIAS("STACK", m_sram)

#include "common/plo-sparc.lds"

Expand Down