-
Notifications
You must be signed in to change notification settings - Fork 109
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add ARM v6 syscalls and Raspberry Pi Pico / Nano Rp2040 Connect #381
Add ARM v6 syscalls and Raspberry Pi Pico / Nano Rp2040 Connect #381
Conversation
|
For reference, I posted rust-lang/rust#90796 (comment) because it seems off to me that asm! does not allow clobbering r8+ on cortex-m0 |
I think I modified the code according to your suggestions, but I am not sure. |
It seems that running an application on Cortex-M0+ faults after the first memop syscall. I modified some asm startup code just to call some other system calls and the kernel seems to lock up. This is the fault the I get using the original asm code. It seems that registers r4-r7 are reset to 0 after the system call.
It seems to fault around here https://github.com/WyliodrinEmbeddedIoT/libtock-rs/blob/b4db50aec1ea0b61af90d25cfba938de0468d4fa/runtime/asm/asm_arm.S#L63. This is a little strange as calling the following code seems to gave the correct value for r5. mov r0, #0 /* operation: set break */
ldr r1, [r5, #4] /* rt_header`s initial process break */
svc 5 /* call `memop` */
mov r0, #0 /* operation: set break */
ldr r1, [r5, #4] /* rt_header`s initial process break */
svc 5 /* call `memop` */
mov r0, #0 /* operation: set break */
ldr r1, [r5, #4] /* rt_header`s initial process break */
svc 5 /* call `memop` */ @hudson-ayers can you take a look at both the kernel and libtock-rs code asm code? I think you might have a better idea than me. |
@alexandruradovici I believe that |
I wonder why the instruction was compiled. Using #383 seems to at least point out the error.
|
IIRC, prior to #383 we don't even tell the assembler which version of ARM/Thumb we are compiling for, so it will presumably compile any instruction that is valid for any chip that supports Thumb. I went ahead and merged #383, as you will need to adjust the assembly to avoid the |
I already did the adjustments, I just need to test them and I'll submit the PR. |
50c5117
to
39cbb9c
Compare
I added a separate file for the armv6 code and included it conditionally. Considering that the only changes are two |
I think you should just change them in the original ARM file and drop the conditional include. Add a note in a comment at the top of the file (there's no room to do it inline) pointing out the waste on ARM v7, so that if someone needs to shave 4 bytes they know where to look. |
Done |
bors r+ |
I just learned about this `asm!` feature, which prompted me to look at whether we were using it. Not sure if some of the others were options when #381 was written, but strictly speaking arm cores are defined to follow the `AAPCS` on exception entry/exit. In practice, I _think_ `C` and `aapcs` (and the others here) are just aliases that do the same thing. Nonetheless, just in case, we should probably put the 'most correct' name here. Relevant doc: https://doc.rust-lang.org/nightly/reference/inline-assembly.html#abi-clobbers
This PR adds support for ARM v6 and the layouts for Raspberry Pi Pico and Arduino Nano RP2040 Connect.
Due to Thumb-1,
asm!
cannot use registers higher than r7, which is a problem foryield1
andyield2
.I used
clobber_abi("C")
for Thumb-1, but I'm not sure it makes sens. It seems to me that there is no difference in the disassembly (with and without the clobber), at least in the examples that I used.