RISC-V Linux SoC, marchID: 0x2b
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Updated
Sep 19, 2024 - C
RISC-V Linux SoC, marchID: 0x2b
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Verilog VPI module to dump FST (Fast Signal Trace) databases
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
Simple microprocessor in SystemVerilog.
System for Cyclone IV FPGA dev board that consist of RISC-V CPU, custom OS, DMA, controllers and drivers for peripherals.
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
The traffic speed control system for the MetroTechno systems set.
The speeding violations control system for the MetroTechno systems set.
special microprocessor design
Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.
HF-RISC SoC
The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure
Minimal SoC design for alarm clock
SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.
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