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Issues list

Question about the sizes of cache L2 & L1
#109 by phillippZZ was closed Jun 18, 2024
2
Accessing addr 0x0000001e doesn't throw access fault exception
#108 by zhangkanqi was closed Jun 1, 2024
3
[Bug Report] Executing sfence.vma under U-mode doesn't throw illegal inst exception
#106 by zhangkanqi was closed May 30, 2024
Wrong value of sie after trapping store_access_fault
#105 by zhangkanqi was closed May 30, 2024
1
Read data incorrectly when executing c.lwsp instruction
#104 by zhangkanqi was closed May 30, 2024
9
Does NaxRicv support S-mode?
#103 by zhangkanqi was closed May 29, 2024
12
How to customize hardware architecture
#102 by phillippZZ was closed Jun 10, 2024
15
NaxRiscv sets sepc[0]=1 which is against the riscv privileged spec
#101 by zhangkanqi was closed May 31, 2024
3
NaxRiscv gets the wrong value when reading from scause
#100 by zhangkanqi was closed May 23, 2024
4
An exception arose when reading instructions from the ELF file
#99 by zhangkanqi was closed May 29, 2024
15
Problems about debug and Halt the Nax
#98 by xie-1399 was closed May 16, 2024
8
Non blocking cache
#97 by SoCSavant was closed Jun 14, 2024
6
L1 cache communication with CPU core
#94 by SoCSavant was closed Jun 14, 2024
Memfilter and interface/Tilelink channel communicating with L2 cache and Memfilter
#93 by SoCSavant was closed Jun 14, 2024
The mmu_sv39.elf fail with SocSim
#88 by Bill94l was closed Jun 22, 2024
18
LINUX on Litex_NaxRISCV ( Linux-capable, RISC-V-based SoC )
#86 by SoCSavant was closed Mar 21, 2024
17
Wrong mask for 64 bits IO access in NaxRiscvProbe
#84 by Bill94l was closed Mar 6, 2024
1
Hi,can you privide an example?
#82 by duanjiulon was closed Apr 25, 2024
56
ext/NaxSoftware/init.sh not up-to-date
#77 by Bill94l was closed Jan 18, 2024
1
Drawing the cache architecture
#76 by SoCSavant was closed Jun 14, 2024
1
cache WB (Writeback) counter increment when reading cache line and D refill counter when writing into cache line
#75 by SoCSavant was closed Jun 14, 2024
26
Loop when change GShare RAM
#73 by zyn810039594 was closed Jan 14, 2024
2
RVLS and testsGen.py
#70 by Bill94l was closed Jun 22, 2024
6
64 bit risc v core from tilelink/socSim.scala.
#68 by SoCSavant was closed Nov 14, 2023
11
[Performance bug] Incorrect register dependency tracking
#67 by ronan-lashermes was closed Nov 14, 2023
5
ProTip! no:milestone will show everything without a milestone.