Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Script for generating SVD and C-headers #25

Merged
merged 46 commits into from
Aug 1, 2021
Merged

Script for generating SVD and C-headers #25

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
46 commits
Select commit Hold shift + click to select a range
1169dbf
Add: scripts to scan ghidra generated source
Yangff Jul 19, 2021
ba0d3ce
library to interactively generate SVD and C-header
Yangff Jul 19, 2021
79f076d
Add: Manually extracted reg defines for mdm and partially agc, based …
Yangff Jul 19, 2021
0b8f6ce
reg maps generated by the scripts
Yangff Jul 19, 2021
1e6cbfb
Parse CEVA style comment to generate reg map
Yangff Jul 19, 2021
8505639
Support for interruption
Yangff Jul 19, 2021
ac07f8d
add missing header from latest sdk
Yangff Jul 20, 2021
24b868f
add another missing header
Yangff Jul 20, 2021
4b1e950
add other registers
Yangff Jul 20, 2021
6aa398a
support Bouffalolab style comment
Yangff Jul 20, 2021
1c4c454
generate headers
Yangff Jul 20, 2021
ad259d9
add gain regs
Yangff Jul 20, 2021
07078da
add agc_config code for scan
Yangff Jul 21, 2021
5a49ad2
scan agc
Yangff Jul 21, 2021
d5db576
allow duplicate field for better scanning
Yangff Jul 21, 2021
6c6e5c7
should not mix @breif and @name for alios style and Bouffalolab
Yangff Jul 21, 2021
dd21c20
fix problem with different style header
Yangff Jul 21, 2021
da5ccc9
update agc.h result
Yangff Jul 21, 2021
ada7467
update header format
Yangff Jul 21, 2021
347e5c0
fix dup name
Yangff Jul 21, 2021
2414e04
return field after added
Yangff Jul 21, 2021
cdc3eb9
add more reg from phy_bl602.o
Yangff Jul 21, 2021
45e4118
update mdm.h with regs found in phy_bl602.o
Yangff Jul 21, 2021
42c4e98
add missing bit
Yangff Jul 21, 2021
f15b976
add bit
Yangff Jul 21, 2021
974fe26
add missing rxndpnstsmax
Yangff Jul 21, 2021
d18fd82
support parse bl svd file and find reg with addr and mask
Yangff Jul 22, 2021
5f58860
add bz_phyfunc
Yangff Jul 22, 2021
ec27cd6
add bz_phy.h
Yangff Jul 22, 2021
0dc58f2
add support for 0x
Yangff Jul 22, 2021
dc056a2
format fix
Yangff Jul 22, 2021
5f5e117
more stable name
Yangff Jul 23, 2021
833e83c
add extra information from DWARF
Yangff Jul 24, 2021
ca4abf8
add extra names
Yangff Jul 24, 2021
a3a7308
import other DWARF info and done
Yangff Jul 24, 2021
f2b7fc3
padding to 32
Yangff Jul 24, 2021
d992280
done
Yangff Jul 24, 2021
5cad578
put irqmacccatimeouten as field name
Yangff Jul 24, 2021
0d958c1
fix agc
Yangff Jul 24, 2021
b2ffe27
add scanner for new sources
Yangff Jul 26, 2021
a723f9d
add new sources
Yangff Jul 26, 2021
7898731
update scan result
Yangff Jul 26, 2021
fb1efea
add svd argument
Yangff Jul 26, 2021
ae66bdf
add generated svds
Yangff Jul 26, 2021
f1ea6bd
add scanner for rf
Yangff Jul 26, 2021
47933fa
add fixed svd file, fix reg name bug in svd2c
Yangff Jul 26, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
update scan result
  • Loading branch information
@Yangff
Yangff committed Jul 26, 2021
commit 7898731679e83dee8e1902ed62572abab760befb
146 changes: 134 additions & 12 deletions src/include/phy/agc.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -224,61 +224,130 @@ typedef union {
uint32_t pad0 : 15;
uint32_t rc2_rx0_vga_idx_min : 5; // @ 19 -- 15 # 0xfff07fff
uint32_t rc2_rx0_vga_idx_max : 5; // @ 24 -- 20 # 0xfe0fffff
uint32_t pad1 : 7;
uint32_t rc2_rx0_vga_gain_min_db : 6; // @ 30 -- 25 # 0x81ffffff
uint32_t rc2_rx0_vga_approx_mode : 1; // @ 31 -- 31 # 0x7fffffff
};
} r0xc040; // @ 0x1040
union {
uint32_t value;
struct {
uint32_t rc2_rx0_lna_idx_min : 8; // @ 7 -- 0 # 0xffffff00
uint32_t rc2_rx0_lna_idx_max : 8; // @ 15 -- 8 # 0xffff00ff
uint32_t pad0 : 16;
uint32_t rc2_rx0_lna_idx : 8; // @ 23 -- 16 # 0xff00ffff
uint32_t pad0 : 8;
};
} r0xc044; // @ 0x1044
uint8_t pad12[0x38];
uint8_t rxgain_offset_vs_temperature[0x9]; // @ 0x1080
uint8_t pad13[0x194];
uint8_t pad13[0xfc];
union {
uint32_t value;
struct {
uint32_t rc2_rx0_nf_gain_0 : 6; // @ 5 -- 0 # 0xffffffc0
uint32_t pad0 : 2;
uint32_t rc2_rx0_nf_gain_1 : 6; // @ 13 -- 8 # 0xffffc0ff
uint32_t pad1 : 2;
uint32_t rc2_rx0_nf_gain_2 : 6; // @ 21 -- 16 # 0xffc0ffff
uint32_t pad2 : 2;
uint32_t rc2_rx0_nf_gain_3 : 6; // @ 29 -- 24 # 0xc0ffffff
uint32_t pad3 : 2;
};
} r0xc180; // @ 0x1180
union {
uint32_t value;
struct {
uint32_t rc2_rx0_nf_gain_4 : 6; // @ 5 -- 0 # 0xffffffc0
uint32_t pad0 : 2;
uint32_t rc2_rx0_nf_gain_5 : 6; // @ 13 -- 8 # 0xffffc0ff
uint32_t pad1 : 2;
uint32_t rc2_rx0_nf_gain_6 : 6; // @ 21 -- 16 # 0xffc0ffff
uint32_t pad2 : 2;
uint32_t rc2_rx0_nf_gain_7 : 6; // @ 29 -- 24 # 0xc0ffffff
uint32_t pad3 : 2;
};
} r0xc184; // @ 0x1184
union {
uint32_t value;
struct {
uint32_t rc2_rx0_nf_gain_8 : 6; // @ 5 -- 0 # 0xffffffc0
uint32_t pad0 : 26;
};
} r0xc188; // @ 0x1188
uint8_t pad14[0x8c];
union {
uint32_t value;
struct {
uint32_t txhbf20coeffsel : 16; // @ 15 -- 0 # 0xffff0000
uint32_t pad0 : 16;
};
} rc218; // @ 0x1218
uint8_t pad14[0x5f8];
uint8_t pad15[0x5e4];
union {
uint32_t value;
struct {
uint32_t rc2_fe0dcest_dly_num_40 : 4; // @ 3 -- 0 # 0xfffffff0
uint32_t rc2_fe0dcest_dly_ena_40 : 1; // @ 4 -- 4 # 0xffffffef
uint32_t pad0 : 3;
uint32_t rc2_fe0dcest_dly_num_20 : 4; // @ 11 -- 8 # 0xfffff0ff
uint32_t rc2_fe0dcest_dly_ena_20 : 1; // @ 12 -- 12 # 0xffffefff
uint32_t pad1 : 3;
uint32_t rc2_feadc0_dly_num : 3; // @ 18 -- 16 # 0xfff8ffff
uint32_t rc2_feadc0_dly_ena : 1; // @ 19 -- 19 # 0xfff7ffff
uint32_t pad2 : 10;
uint32_t rc2_rx_ramp_ctrl : 2; // @ 31 -- 30 # 0x3fffffff
};
} r0xc800; // @ 0x1800
uint8_t pad16[0x8];
union {
uint32_t value;
struct {
uint32_t pad0 : 24;
uint32_t rc2_txdsssdiggainlin0 : 8; // @ 31 -- 24 # 0xffffff
};
} r0xc80c; // @ 0x180c
uint8_t pad17[0x4];
union {
uint32_t value;
struct {
uint32_t rc2_pkdet_mode : 2; // @ 1 -- 0 # 0xfffffffc
uint32_t rc2_pkdet_cnt_thr : 4; // @ 5 -- 2 # 0xffffffc3
uint32_t pad0 : 26;
uint32_t rc2_pkdet_cnt_win : 4; // @ 9 -- 6 # 0xfffffc3f
uint32_t pad0 : 22;
};
} r0xc814; // @ 0x1814
uint8_t pad15[0x14];
uint8_t pad18[0x14];
union {
uint32_t value;
struct {
uint32_t rc2_inbdpow_adj_thr_dbm : 8; // @ 7 -- 0 # 0xffffff00
uint32_t rc2_inbdpowsupthr_adj_en : 1; // @ 8 -- 8 # 0xfffffeff
uint32_t pad0 : 2;
uint32_t rc2_inbdpowsupthr_adj_step : 2; // @ 10 -- 9 # 0xfffff9ff
uint32_t rc2_inbdpowinfthr_adj_en : 1; // @ 11 -- 11 # 0xfffff7ff
uint32_t pad1 : 3;
uint32_t rc2_inbdpowinfthr_adj_step : 2; // @ 13 -- 12 # 0xffffcfff
uint32_t rc2_inbdpowfastvalid_en : 1; // @ 14 -- 14 # 0xffffbfff
uint32_t rc2_inbdpowfastvalid_cnt : 9; // @ 23 -- 15 # 0xff007fff
uint32_t pad2 : 8;
uint32_t pad0 : 8;
};
} r0xc82c; // @ 0x182c
union {
uint32_t value;
struct {
uint32_t pad0 : 10;
uint32_t rc2_evt4tgtadd : 9; // @ 8 -- 0 # 0xfffffe00
uint32_t pad0 : 1;
uint32_t rc2_evt4opcomb : 3; // @ 12 -- 10 # 0xffffe3ff
uint32_t pad1 : 1;
uint32_t rc2_evt4pathcomb : 1; // @ 13 -- 13 # 0xffffdfff
uint32_t rc2_evt4op3 : 6; // @ 19 -- 14 # 0xfff03fff
uint32_t rc2_evt4op2 : 6; // @ 25 -- 20 # 0xfc0fffff
uint32_t rc2_evt4op1 : 6; // @ 31 -- 26 # 0x3ffffff
};
} r0xc830; // @ 0x1830
uint8_t pad16[0x4];
union {
uint32_t value;
struct {
uint32_t rc2_adcpowinsel : 2; // @ 1 -- 0 # 0xfffffffc
uint32_t pad0 : 30;
};
} r0xc834; // @ 0x1834
union {
uint32_t value;
struct {
Expand All @@ -303,6 +372,59 @@ typedef union {
uint32_t rc2_reflevdssscontthd_en : 1; // @ 31 -- 31 # 0x7fffffff
};
} r0xc840; // @ 0x1840
union {
uint32_t value;
struct {
uint32_t rc2_agcrampupthr1 : 14; // @ 13 -- 0 # 0xffffc000
uint32_t pad0 : 2;
uint32_t rc2_agcrampupthr2 : 14; // @ 29 -- 16 # 0xc000ffff
uint32_t pad1 : 2;
};
} r0xc844; // @ 0x1844
union {
uint32_t value;
struct {
uint32_t rc2_agcrampupthr3 : 14; // @ 13 -- 0 # 0xffffc000
uint32_t pad0 : 18;
};
} r0xc848; // @ 0x1848
union {
uint32_t value;
struct {
uint32_t rc2_agcrampupcorrect1 : 8; // @ 7 -- 0 # 0xffffff00
uint32_t rc2_agcrampupcorrect2 : 8; // @ 15 -- 8 # 0xffff00ff
uint32_t rc2_agcrampupcorrect3 : 8; // @ 23 -- 16 # 0xff00ffff
uint32_t pad0 : 7;
uint32_t rc2_agcrampupcorrecten : 1; // @ 31 -- 31 # 0x7fffffff
};
} r0xc84c; // @ 0x184c
uint8_t pad19[0xb0];
union {
uint32_t value;
struct {
uint32_t rc2_sts_agc_gain_target0 : 8; // @ 7 -- 0 # 0xffffff00
uint32_t pad0 : 24;
};
} r0xc900; // @ 0x1900
union {
uint32_t value;
struct {
uint32_t pad0 : 16;
uint32_t rc2_sts_rx0_rbb_cfg_idx : 5; // @ 20 -- 16 # 0xffe0ffff
uint32_t pad1 : 3;
uint32_t rc2_sts_rx0_lna_gain_idx : 8; // @ 31 -- 24 # 0xffffff
};
} r0xc904; // @ 0x1904
union {
uint32_t value;
struct {
uint32_t rc2_sts_rx0_nf_gain : 6; // @ 5 -- 0 # 0xffffffc0
uint32_t pad0 : 2;
uint32_t rc2_sts_rx0_total_gain_db_s : 8; // @ 15 -- 8 # 0xffff00ff
uint32_t rc2_sts_rx0_vga_gain_db_s : 8; // @ 23 -- 16 # 0xff00ffff
uint32_t rc2_sts_rx0_lna_gain_db_s : 8; // @ 31 -- 24 # 0xffffff
};
} r0xc908; // @ 0x1908
};
} agc_regs;
#define AGC_BASE 0x44c0b000
Expand Down
Loading