Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Script for generating SVD and C-headers #25

Merged
merged 46 commits into from
Aug 1, 2021
Merged
Changes from 1 commit
Commits
Show all changes
46 commits
Select commit Hold shift + click to select a range
1169dbf
Add: scripts to scan ghidra generated source
Yangff Jul 19, 2021
ba0d3ce
library to interactively generate SVD and C-header
Yangff Jul 19, 2021
79f076d
Add: Manually extracted reg defines for mdm and partially agc, based …
Yangff Jul 19, 2021
0b8f6ce
reg maps generated by the scripts
Yangff Jul 19, 2021
1e6cbfb
Parse CEVA style comment to generate reg map
Yangff Jul 19, 2021
8505639
Support for interruption
Yangff Jul 19, 2021
ac07f8d
add missing header from latest sdk
Yangff Jul 20, 2021
24b868f
add another missing header
Yangff Jul 20, 2021
4b1e950
add other registers
Yangff Jul 20, 2021
6aa398a
support Bouffalolab style comment
Yangff Jul 20, 2021
1c4c454
generate headers
Yangff Jul 20, 2021
ad259d9
add gain regs
Yangff Jul 20, 2021
07078da
add agc_config code for scan
Yangff Jul 21, 2021
5a49ad2
scan agc
Yangff Jul 21, 2021
d5db576
allow duplicate field for better scanning
Yangff Jul 21, 2021
6c6e5c7
should not mix @breif and @name for alios style and Bouffalolab
Yangff Jul 21, 2021
dd21c20
fix problem with different style header
Yangff Jul 21, 2021
da5ccc9
update agc.h result
Yangff Jul 21, 2021
ada7467
update header format
Yangff Jul 21, 2021
347e5c0
fix dup name
Yangff Jul 21, 2021
2414e04
return field after added
Yangff Jul 21, 2021
cdc3eb9
add more reg from phy_bl602.o
Yangff Jul 21, 2021
45e4118
update mdm.h with regs found in phy_bl602.o
Yangff Jul 21, 2021
42c4e98
add missing bit
Yangff Jul 21, 2021
f15b976
add bit
Yangff Jul 21, 2021
974fe26
add missing rxndpnstsmax
Yangff Jul 21, 2021
d18fd82
support parse bl svd file and find reg with addr and mask
Yangff Jul 22, 2021
5f58860
add bz_phyfunc
Yangff Jul 22, 2021
ec27cd6
add bz_phy.h
Yangff Jul 22, 2021
0dc58f2
add support for 0x
Yangff Jul 22, 2021
dc056a2
format fix
Yangff Jul 22, 2021
5f5e117
more stable name
Yangff Jul 23, 2021
833e83c
add extra information from DWARF
Yangff Jul 24, 2021
ca4abf8
add extra names
Yangff Jul 24, 2021
a3a7308
import other DWARF info and done
Yangff Jul 24, 2021
f2b7fc3
padding to 32
Yangff Jul 24, 2021
d992280
done
Yangff Jul 24, 2021
5cad578
put irqmacccatimeouten as field name
Yangff Jul 24, 2021
0d958c1
fix agc
Yangff Jul 24, 2021
b2ffe27
add scanner for new sources
Yangff Jul 26, 2021
a723f9d
add new sources
Yangff Jul 26, 2021
7898731
update scan result
Yangff Jul 26, 2021
fb1efea
add svd argument
Yangff Jul 26, 2021
ae66bdf
add generated svds
Yangff Jul 26, 2021
f1ea6bd
add scanner for rf
Yangff Jul 26, 2021
47933fa
add fixed svd file, fix reg name bug in svd2c
Yangff Jul 26, 2021
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
Support for interruption
  • Loading branch information
Yangff committed Jul 19, 2021
commit 850563968818d83510b5be7a61b32143a2b85622
30 changes: 27 additions & 3 deletions script/reglib.py
Original file line number Diff line number Diff line change
Expand Up @@ -127,13 +127,26 @@ def genSVD(self):
def genHeader(self):
return [f'{self.typename} {self.name}[{hex(self.dim)}]; // @ {hex(self.offset)}']

class ints(gen):
def __init__(self, name, intid):
self.name = name
self.intid = intid
def genSVD(self):
return [
'<interrupt>',
f' <name>{self.name}</name>',
f' <value>{self.intid}</value>',
'</interrupt>'
]

class peripheral(gen):
def __init__(self, name, base, size):
def __init__(self, name, base, size, interrupt=None):
self.name = name
self.base = base
self.size = size
self.regs:List[Union[buf, reg]] = []
self.interrupt = interrupt

def addReg(self, name, addr):
r = self.findReg(addr)
if r:
Expand Down Expand Up @@ -166,9 +179,13 @@ def genSVD(self):
' <offset>0</offset>',
f' <size>{hex(self.size)}</size>',
' <usage>registers</usage>',
' </addressBlock>',
' <registers>'
' </addressBlock>'
]

if self.interrupt:
s.extend(ident(self.interrupt.genSVD(), 1))

s.append(' <registers>')
for i in self.regs:
s.extend(ident(i.genSVD(), 2))
s.append(' </registers>')
Expand Down Expand Up @@ -211,6 +228,13 @@ def Peripheral(p):
context.p = p
return p

def Int(name, irq):
if context.p:
it = context.p.interrupt = ints(name, irq)
return it
else:
print("You are not in any peripheral")

def Reg(name, addr):
if context.p:
r = context.p.addReg(name, addr)
Expand Down