support parse bl svd file and find reg with addr and mask

script/manualext.py

@@ -1,9 +1,12 @@
 #!/usr/bin/env python3
 from reglib import *
+from typing import Mapping
+
+peris :Mapping[str, peripheral] = {}
 
 ############ MDM
 
-Peripheral(peripheral('mdm', 0x44c00000, 0x4000))
+peris['mdm'] = Peripheral(peripheral('mdm', 0x44c00000, 0x4000))
 
 Reg('txchan', 0x44c00824)
 Field('txcbwmax', 0xfcffffff) # Channel bandwidth
@@ -92,16 +95,13 @@
 Reg('r874', 0x44c00874)
 Field('resetto1', 0xf7ffffff)
 Field('set1beforewriteagcmem', 0xdfffffff)
-
-open('../src/include/phy/mdm.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 
 
 ############# AGC
 
-
-Peripheral(peripheral('agc', 0x44c0b000, 0x2000))
+peris['agc'] = Peripheral(peripheral('agc', 0x44c0b000, 0x2000))
 Reg('r000', 0x44c0b000)
 FieldBit('iqcomp', 31-10)
 
@@ -172,15 +172,15 @@ def scan_write(code):
     "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffd);",
     "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);",
 ])
-open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 
-Peripheral(peripheral('agcram', 0x54c0a000, 0x800))
+peris['agcram'] = Peripheral(peripheral('agcram', 0x54c0a000, 0x800))
 Buf('agcram', 0x54c0a000, 0x54c0a800 - 4)
 
-open('../src/include/phy/agcram.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/agcram.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 #
@@ -215,23 +215,23 @@ def getregs(fname, pattern='name'):
 
 
 
-Peripheral(peripheral('mac_core', 0x44b00000, 0x1000))
+peris['mac_core'] = Peripheral(peripheral('mac_core', 0x44b00000, 0x1000))
 
 for code, offset in getregs("../components/bl602/bl602_wifidrv/bl60x_wifi_driver/reg_mac_core.h", pattern='brief'):
     RegFromComment(offset + 0x44b00000, code)
 
-open('../src/include/phy/mac_core.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/mac_core.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 
-Peripheral(peripheral('mac_pl', 0x44b08000, 0x1000))
+peris['mac_pl'] = Peripheral(peripheral('mac_pl', 0x44b08000, 0x1000))
 
 for code, offset in getregs("../alios/mac_pl.h"):
     RegFromComment(offset + 0x44b00000, code)
 
 
-open('../src/include/phy/mac_pl.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/mac_pl.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
@@ -242,7 +242,7 @@ def getregs(fname, pattern='name'):
 ## look txl_payload_handle_backup for more info
 ####
 
-Peripheral(peripheral('dma', 0x44a00000, 0x1000))
+peris['dma'] = Peripheral(peripheral('dma', 0x44a00000, 0x1000))
 
 Reg('status', 0x44a00024)
 Field("TX", 0x1f)
@@ -278,13 +278,13 @@ def getregs(fname, pattern='name'):
 Reg('LinkListItem1', 0x44a000ac)
 FieldBit("lli", 0, 16)
 
-open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 ############# sysctrl
 
-Peripheral(peripheral('sysctrl', 0x44900000, 0x1000))
+peris['sysctrl'] = Peripheral(peripheral('sysctrl', 0x44900000, 0x1000))
 Reg('time', 0x44900084)
 FieldBit('time_greater_on_bit12', 0)
 Reg("sysctrl_r68", 0x44900068) # set to 0x8000000c for init
@@ -298,28 +298,41 @@ def getregs(fname, pattern='name'):
 
 Reg("r074", 0x44900068) # set to b09
 
-open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 
 ############# Wifi Regs 92
 ## wtf is this???
 
-Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000))
+peris['sysctrl92'] = Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000))
 Reg("set5010001f", 0x44920004)
 
-open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
 #print('\n'.join(GenSVD()))
 
 
 ############# Wifi IPC (EMB/Core)
-Peripheral(peripheral('ipc', 0x44800000, 0x1000))
+peris['ipc'] = Peripheral(peripheral('ipc', 0x44800000, 0x1000))
 
 for code, offset in getregs("../components/bl602/bl602_wifidrv/bl60x_wifi_driver/reg_ipc_app.h", pattern='brief'):
     RegFromComment(offset + 0x44800000, code)
 
-open('../src/include/phy/ipc.h', 'w').write('\n'.join(GenHeader()))
+#open('../src/include/phy/ipc.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
-#print('\n'.join(GenSVD()))
+#print('\n'.join(GenSVD()))
+
+if __name__ == '__main__':
+    import sys
+    if len(sys.argv) == 1:
+        for p_name, p in peris.items():
+            open(f"../src/include/phy/{p_name}.h", "w").write("\n".join(p.genHeader()))
+    else:
+        if len(sys.argv) >= 2:
+            addr = int(sys.argv[1], 16)
+            mask = 0
+            if len(sys.argv) == 3:
+                mask = int(sys.argv[2], 16)
+            print(CAccess(peris, addr, mask))

script/reglib.py

@@ -296,6 +296,24 @@ def HasField(addr):
         return context.r.hasField(addr)
     print("You are not in any register")
 
+def CAccess(peris, addr, mask):
+    for p_name, p in peris.items():
+        if p.base <= addr and p.base + p.size >= addr:
+            r = p.findReg(addr)
+            if r:
+                if r.fields:
+                    if mask == 0:
+                        return f"{p_name.upper()}->{r.name}.value"
+                    else:
+                        f = r.hasField(mask)
+                        if f:
+                            return f"{p_name.upper()}->{r.name}.{f.name}"
+                        else:
+                            return f"({p_name.upper()}->{r.name}.value) & {hex(mask)}"
+                else:
+                    return f"{p_name.upper()}->{r.name}"
+
+
 def RegFromComment(addr, comment:str):
     name = ""
     import re

script/svd2c.py

@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+import xml.etree.ElementTree as ET
+from reglib import *
+from typing import Mapping
+
+peris :Mapping[str, peripheral] = {}
+
+import pickle, os
+if os.path.exists("./peris.cache"):
+    peris = pickle.load(open("./peris.cache", "rb"))
+else:
+    tree = ET.parse('../components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd')
+
+    root = tree.getroot()
+
+    for p in root.iter('peripheral'):
+        p_name = p.find('name').text
+        baseAddress = int(p.find('baseAddress').text, 16)
+        addressSize = int(p.find('./addressBlock/size').text, 16)
+
+        pp = Peripheral(peripheral(p_name, baseAddress, addressSize))
+        for r in p.iter('register'):
+            r_name = r.find('name').text
+            r_offset = int(r.find('addressOffset').text, 16)
+            Reg(r_name, r_offset + baseAddress)
+            for f in p.iter('field'):
+                f_name = f.find('name').text
+                lsb = int(f.find('lsb').text)
+                msb = int(f.find('msb').text)
+                FieldBit(f_name, lsb, msb - lsb + 1)
+        peris[p_name] = pp
+    pickle.dump(peris, open("./peris.cache", "wb"))
+
+if __name__ == '__main__':
+    import sys
+    if len(sys.argv) == 1:
+        for p_name, p in peris.items():
+            open(f"../src/include/soc/{p_name}.h", "w").write("\n".join(p.genHeader()))
+    else:
+        if len(sys.argv) >= 2:
+            addr = int(sys.argv[1], 16)
+            mask = 0
+            if len(sys.argv) == 3:
+                mask = int(sys.argv[2], 16)
+            print(CAccess(peris, addr, mask))