lowRISC / ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Generic Register Interface (contains various adapters)
SystemVerilog modules and classes commonly used for verification
Common SystemVerilog components
RISC-V Debug Support for our PULP RISC-V Cores
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI Adapter(s) for RISC-V Atomic Operations
OpenTitan: Open source silicon root of trust
A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6