TinyTapeout / tt07-verilog-template
Submission template for Tiny Tapeout 7 - Verilog HDL Projects
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Submission template for Tiny Tapeout 7 - Verilog HDL Projects
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
A collection of Master XDC files for Digilent FPGA and Zynq boards.
A gorgeous theme for Tkinter/ttk, based on the Sun Valley visual style ✨