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Support for single bit coarse cells. Option for debug prints.
#433
opened Oct 9, 2017 by
Kmanfi
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updated Mar 21, 2024
cleaning enhancements see #2048
#2049
opened May 14, 2020 by
gojimmypi
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updated Mar 21, 2024
Add support for unpacked arrays assignment
#2331
opened Aug 5, 2020 by
kgugala
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updated Mar 21, 2024
gowin: Fix cells_sim.v to make abc9 work
#2391
opened Sep 27, 2020 by
tpambor
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updated Mar 21, 2024
Adds support for defining the YOSYS_DATDIR location at runtime
#2417
opened Oct 29, 2020 by
QuantamHD
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updated Mar 21, 2024
proc_prune: do not promote partially redundant assignments.
#2458
opened Nov 28, 2020 by
jfng
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updated Mar 21, 2024
ice40: simulate SPRAM poweron delay in cells_sim
#2471
opened Dec 3, 2020 by
sapphire-arches
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updated Mar 21, 2024
Changes to Liberty parser to make it more permissive of paranthetical expressions and keeper cells
#2503
opened Dec 24, 2020 by
jrrk2
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updated Mar 21, 2024
quicklogic: add PolarPro3 BRAM inference
#2703
opened Mar 25, 2021 by
Ravenslofty
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updated Mar 21, 2024
Revert "Merge pull request #641 from tklam/master"
#2740
opened Apr 28, 2021 by
clairexen
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updated Mar 21, 2024
firrtl: Add support for yosys' $lut cell
#2994
opened Sep 1, 2021 by
sahandKashani
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updated Mar 21, 2024
Fix global cache destruction in IdString class
#3081
opened Nov 18, 2021 by
Icenowy
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updated Mar 21, 2024
ecp5: map reduce_{and/or} to carry chains
#3161
opened Jan 17, 2022 by
Ravenslofty
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updated Mar 21, 2024
abc9: break conflict between boxes and outputs
#3311
opened May 10, 2022 by
Ravenslofty
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updated Mar 21, 2024
Add parsing of verilog module port aliases (fixes #3334)
discuss
to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/)
#3339
opened May 24, 2022 by
hansfbaier
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updated Mar 21, 2024
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