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Issues list

SystemVerilog Preprocessor help wanted Extra attention is needed preprocessor anything related to preprocessing (conditionals, macros, etc.)
#183 opened Feb 5, 2020 by fangism
👍 7
Forbid implicit declarations style-linter Verilog style-linter issues
#217 opened Feb 23, 2020 by corco
1
3 👍 5
Add Support for CMake Build System
#876 opened Aug 1, 2021 by AndruePeters
👍 5
feature request: formatter config formatter Verilog code formatter issues
#752 opened Apr 10, 2021 by alessandroaimar
@pawelsag
👍 4
The first macro get blamed for any syntax issues in the file language-server Language server related issues
#2042 opened Dec 13, 2023 by KarelPeeters
👍 4
Add support for configuration files describing formatter style enhancement New feature or request formatter Verilog code formatter issues
#898 opened Aug 27, 2021 by mglb
3 👍 4
Port not completely aligned when input/output var logic xxxx formatter Verilog code formatter issues
#1980 opened Jul 24, 2023 by zhutmost
👍 4
Aligning port declarations formatter Verilog code formatter issues
#1217 opened Feb 24, 2022 by ariyonaty
2 👍 3
wire logic foo is rejected rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#397 opened Aug 7, 2020 by zcold
1 👍 3
Option to have alignment only apply to blocks of code formatter Verilog code formatter issues
#1832 opened Mar 24, 2023 by patrickrst
1 👍 2
[Feature request] Support to add spaces in parentheses/emptyblock/emptyparentheses with formatter formatter Verilog code formatter issues
#2054 opened Dec 18, 2023 by beyond-fu
👍 2
[Help or suggestion] How to disable short if-else statements on a single line? formatter Verilog code formatter issues
#2053 opened Dec 18, 2023 by beyond-fu
3 👍 2
No Highlight in VSCode enhancement New feature or request style-linter Verilog style-linter issues
#1363 opened Jul 15, 2022 by liuwuhaoo
2 👍 2
GNU autotools build build system matters pertaining to building Verible enhancement New feature or request
#4 opened Nov 12, 2019 by fangism
@fangism
👍 2
LSP: provide some template expansion features
#1557 opened Dec 13, 2022 by hzeller
@kbieganski
1 👍 2
Integrate with FuseSoC package management General support for external package managers
#1 opened Nov 12, 2019 by mithro
4 👍 1
alternate style support for formatter [atkenny15] formatter Verilog code formatter issues question Further information is requested
#160 opened Jan 30, 2020 by fangism
4 👍 1
[Feature Req] port alignment formatter Verilog code formatter issues
#1120 opened Dec 10, 2021 by CannedGrape
5 👍 1
Problem with verible-verilog-ls attaching in neovim formatter Verilog code formatter issues
#1342 opened Jun 2, 2022 by r2com
4 👍 1
Formatting parameter and localparameter is not working formatter Verilog code formatter issues
#1254 opened Mar 7, 2022 by henry-hsieh
👍 1
Add prebuilt ARM binaries to releases releases binary release packages
#849 opened Jun 5, 2021 by 0-issue
1 👍 1
Integration of verilog_format into various editors (how-to documentation) documentation Improvements or additions to documentation formatter Verilog code formatter issues help wanted Extra attention is needed
#191 opened Feb 11, 2020 by fangism
👍 1
declaration assignment for unpacked array of packed array rejected rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1183 opened Feb 7, 2022 by matlupi
👍 1
[Feature Req] instantiation alignment formatter Verilog code formatter issues
#1119 opened Dec 10, 2021 by CannedGrape
4 👍 1
comment aligment formatter Verilog code formatter issues
#830 opened May 22, 2021 by somyadashora
2 👍 1
ProTip! Updated in the last three days: updated:>2024-06-26.