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Issues list

alternate style support for formatter [atkenny15] formatter Verilog code formatter issues question Further information is requested
#160 opened Jan 30, 2020 by fangism
4
Provide simple file-list flag
#15 opened Nov 20, 2019 by hzeller
2
[tabular] Handling of tabular alignment formatter Verilog code formatter issues
#28 opened Nov 25, 2019 by msfschaffner
@fangism
4
[line breaks, wraps] Multiline parameter break tuning formatter Verilog code formatter issues
#33 opened Nov 25, 2019 by msfschaffner
3
[line breaks, wraps] Line break tuning formatter Verilog code formatter issues
#36 opened Nov 26, 2019 by msfschaffner
7
Create make format target
#71 opened Dec 3, 2019 by kgugala
@hzeller
On kokoro send build results from bazel directly
#76 opened Dec 3, 2019 by mithro
[style] OT-style differences question Further information is requested
#92 opened Dec 16, 2019 by msfschaffner
2 tasks done
1
[line breaks, spaces] Covergroup/function formatting formatter Verilog code formatter issues
#96 opened Dec 16, 2019 by msfschaffner
2
Syntax error within SV macros preprocessor anything related to preprocessing (conditionals, macros, etc.)
#102 opened Dec 17, 2019 by msfschaffner
9
Verilog dialect support for lint rules (Verilog2009 vs. SystemVerilog2017) enhancement New feature or request style-linter Verilog style-linter issues
#141 opened Jan 20, 2020 by fangism
2
Parse ANSI-style udp_declaration_port_list in UDP declarations rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#149 opened Jan 22, 2020 by fangism
1
Integrate with FuseSoC package management General support for external package managers
#1 opened Nov 12, 2019 by mithro
4
hide direct indexing into subtree structures behind functions in CST library code health improving readability, consistency, test-ability, clean interfaces and abstraction boundaries, etc. help wanted Extra attention is needed
#159 opened Jan 29, 2020 by fangism
VHDL Support enhancement New feature or request help wanted Extra attention is needed
#174 opened Feb 4, 2020 by GCHQDeveloper560
1
Reduce number of options for partition operations in verilog/formatting/tree_unwrapper.cc code health improving readability, consistency, test-ability, clean interfaces and abstraction boundaries, etc. formatter Verilog code formatter issues
#181 opened Feb 5, 2020 by fangism
@fangism
1
SystemVerilog Preprocessor help wanted Extra attention is needed preprocessor anything related to preprocessing (conditionals, macros, etc.)
#183 opened Feb 5, 2020 by fangism
SystemVerilog Abstract Syntax Tree (AST) help wanted Extra attention is needed
#184 opened Feb 5, 2020 by fangism
2
Integration of verilog_format into various editors (how-to documentation) documentation Improvements or additions to documentation formatter Verilog code formatter issues help wanted Extra attention is needed
#191 opened Feb 11, 2020 by fangism
[tests] Update CST tests to check for tokens precisely code health improving readability, consistency, test-ability, clean interfaces and abstraction boundaries, etc.
#208 opened Feb 19, 2020 by fangism
@fangism
2
Forbid implicit declarations style-linter Verilog style-linter issues
#217 opened Feb 23, 2020 by corco
1
3
makedepend-style output preprocessor anything related to preprocessing (conditionals, macros, etc.)
#221 opened Feb 28, 2020 by jdanders
3
Failure to parse if/else macros in always block headers preprocessor anything related to preprocessing (conditionals, macros, etc.)
#228 opened Mar 11, 2020 by imphil
6
Proposal: enhance handling of conditional preprocessor directives enhancement New feature or request help wanted Extra attention is needed preprocessor anything related to preprocessing (conditionals, macros, etc.)
#241 opened Mar 25, 2020 by pmaupin
2
Dynamic code with macros is not parsed properly rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2197 opened Jun 11, 2024 by bhappel-ciena
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