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Issues list

[Help or suggestion] How to disable short if-else statements on a single line? formatter Verilog code formatter issues
#2053 opened Dec 18, 2023 by beyond-fu updated Jun 26, 2024
3
Dynamic code with macros is not parsed properly rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2197 opened Jun 11, 2024 by bhappel-ciena updated Jun 11, 2024
systemverilog interface module definitions can not be found language-server Language server related issues
#2196 opened Jun 11, 2024 by bhappel-ciena updated Jun 11, 2024
verible-verilog-format crashing formatter Verilog code formatter issues
#2189 opened Jun 3, 2024 by joaovam updated Jun 3, 2024
Formatter unable to recognize class instantiation with parameter override inside a struct/union formatter Verilog code formatter issues
#2184 opened May 22, 2024 by brendany1990 updated May 22, 2024
What is the current state of spaces in the preprocessor rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2183 opened May 22, 2024 by The-MEO updated May 22, 2024
Verible formatter fails when third line of port list is blank formatter Verilog code formatter issues
#2182 opened May 16, 2024 by paul-demo updated May 16, 2024
1
linter cannot find macro defined in a different file style-linter Verilog style-linter issues
#2173 opened May 4, 2024 by samimia-swks updated May 11, 2024
3
All features, can add the option to accept the contents of the file without having to pass in one file at a time.
#2170 opened Apr 27, 2024 by 17Reset updated May 11, 2024
1
Feature Request: do not add spaces around logical keywords formatter Verilog code formatter issues
#2179 opened May 7, 2024 by ewolff96 updated May 7, 2024
VSCode - Generate and maintain verible.filelist language-server Language server related issues
#2177 opened May 7, 2024 by sconwayaus updated May 7, 2024
Developing custom verible linting rules for my organization? style-linter Verilog style-linter issues
#1999 opened Aug 14, 2023 by Lightborne updated May 6, 2024
4
Migrate name style rules to regex enhancement New feature or request style-linter Verilog style-linter issues
#2074 opened Jan 13, 2024 by IEncinas10 updated May 5, 2024
10 tasks
@IEncinas10
4
issue with installation
#2018 opened Sep 26, 2023 by gauthamsaiv updated May 3, 2024
1
automatically comment preprocessor conditionals enhancement New feature or request good first issue Good for newcomers preprocessor anything related to preprocessing (conditionals, macros, etc.) style-linter Verilog style-linter issues
#2171 opened Apr 30, 2024 by fangism updated Apr 30, 2024
Parser rejects streaming operators that use the "with" clause rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2167 opened Apr 19, 2024 by fpgauserdude updated Apr 19, 2024
Repeated Diagnostic Messages in coc.nvim with Verible Language Server language-server Language server related issues
#2164 opened Apr 18, 2024 by TBD9rain updated Apr 19, 2024
3
nix package for mac not available
#2163 opened Apr 16, 2024 by thuvasooriya updated Apr 16, 2024
[unpacked-dimensions-range-ordering] - configuration enhancement New feature or request style-linter Verilog style-linter issues
#2161 opened Apr 16, 2024 by sconwayaus updated Apr 16, 2024
verible-verilog-obfuscate crashes when program has pragma directive rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2159 opened Apr 15, 2024 by rafasumi updated Apr 15, 2024
Long localparam lines are not formatted formatter Verilog code formatter issues
#2156 opened Apr 12, 2024 by goekce updated Apr 15, 2024
1
Return type using type(...) throws syntax error rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2157 opened Apr 12, 2024 by goekce updated Apr 12, 2024
Forbid implicit begin/end enhancement New feature or request style-linter Verilog style-linter issues
#1321 opened Apr 26, 2022 by suzizecat updated Apr 5, 2024
1
How to use rule for having a begin and end enhancement New feature or request style-linter Verilog style-linter issues
#2040 opened Nov 18, 2023 by muneebullashariff updated Apr 5, 2024
4
verible-verilog-syntax does not fully support `protect directive rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2153 opened Apr 3, 2024 by craigc40 updated Apr 3, 2024
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