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Issues list

GNU autotools build build system matters pertaining to building Verible enhancement New feature or request
#4 opened Nov 12, 2019 by fangism updated Nov 12, 2019
@fangism
Provide simple file-list flag
#15 opened Nov 20, 2019 by hzeller updated Nov 22, 2019
2
[line breaks, wraps] Multiline parameter break tuning formatter Verilog code formatter issues
#33 opened Nov 25, 2019 by msfschaffner updated Nov 26, 2019
3
Create make format target
#71 opened Dec 3, 2019 by kgugala updated Dec 3, 2019
@hzeller
On kokoro send build results from bazel directly
#76 opened Dec 3, 2019 by mithro updated Dec 3, 2019
[line breaks, wraps] Line break tuning formatter Verilog code formatter issues
#36 opened Nov 26, 2019 by msfschaffner updated Dec 16, 2019
7
[line breaks, spaces] Covergroup/function formatting formatter Verilog code formatter issues
#96 opened Dec 16, 2019 by msfschaffner updated Dec 16, 2019
2
Syntax error within SV macros preprocessor anything related to preprocessing (conditionals, macros, etc.)
#102 opened Dec 17, 2019 by msfschaffner updated Jan 10, 2020
9
Parse ANSI-style udp_declaration_port_list in UDP declarations rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#149 opened Jan 22, 2020 by fangism updated Jan 22, 2020
1
Verilog dialect support for lint rules (Verilog2009 vs. SystemVerilog2017) enhancement New feature or request style-linter Verilog style-linter issues
#141 opened Jan 20, 2020 by fangism updated Jan 23, 2020
2
VHDL Support enhancement New feature or request help wanted Extra attention is needed
#174 opened Feb 4, 2020 by GCHQDeveloper560 updated Feb 4, 2020
1
SystemVerilog Preprocessor help wanted Extra attention is needed preprocessor anything related to preprocessing (conditionals, macros, etc.)
#183 opened Feb 5, 2020 by fangism updated Feb 6, 2020
Integration of verilog_format into various editors (how-to documentation) documentation Improvements or additions to documentation formatter Verilog code formatter issues help wanted Extra attention is needed
#191 opened Feb 11, 2020 by fangism updated Feb 11, 2020
Integrate with FuseSoC package management General support for external package managers
#1 opened Nov 12, 2019 by mithro updated Feb 27, 2020
4
makedepend-style output preprocessor anything related to preprocessing (conditionals, macros, etc.)
#221 opened Feb 28, 2020 by jdanders updated Feb 28, 2020
3
Reduce number of options for partition operations in verilog/formatting/tree_unwrapper.cc code health improving readability, consistency, test-ability, clean interfaces and abstraction boundaries, etc. formatter Verilog code formatter issues
#181 opened Feb 5, 2020 by fangism updated Mar 10, 2020
@fangism
1
Failure to parse if/else macros in always block headers preprocessor anything related to preprocessing (conditionals, macros, etc.)
#228 opened Mar 11, 2020 by imphil updated Mar 12, 2020
6
Proposal: enhance handling of conditional preprocessor directives enhancement New feature or request help wanted Extra attention is needed preprocessor anything related to preprocessing (conditionals, macros, etc.)
#241 opened Mar 25, 2020 by pmaupin updated Mar 25, 2020
2
[tests] Update CST tests to check for tokens precisely code health improving readability, consistency, test-ability, clean interfaces and abstraction boundaries, etc.
#208 opened Feb 19, 2020 by fangism updated Mar 31, 2020
@fangism
2
Use OpenTitan dv_macros.svh as a testcase for macro handling formatter Verilog code formatter issues
#251 opened Apr 1, 2020 by msfschaffner updated Apr 4, 2020
8
Syntax error on ')' preceded by a ','
#269 opened Apr 14, 2020 by JakubJatczak updated Apr 14, 2020
1
Syntax error on '==' inside $setuphold rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#270 opened Apr 14, 2020 by JakubJatczak updated Apr 14, 2020
2
Rejects ifdef'd module port declaration line beginning with ',' preprocessor anything related to preprocessing (conditionals, macros, etc.) rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#267 opened Apr 14, 2020 by JakubJatczak updated Apr 15, 2020
4
lexer: preserve encrypted text as tokens, filter them from lint analysis, preserve for formatting
#259 opened Apr 8, 2020 by fangism updated Apr 17, 2020
@fangism
1
EOL-comments in expanded macro args not wrapping properly formatter Verilog code formatter issues
#275 opened Apr 17, 2020 by fangism updated Apr 17, 2020
1
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