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Commits on Nov 21, 2020

• Add misaligned(not tested)

  

  Bohan Hu

  committedNov 21, 2020
  c29054f

• update module names

  

  Bohan Hu

  committedNov 21, 2020
  34cbf1d

Commits on Nov 16, 2020

• Merge pull request #1 from Bohan-hu/3-stage-AXI

  

  Bohan Hu

  authoredNov 16, 2020
  524768c

Commits on Nov 14, 2020

• fixed initial state

  

  Bohan Hu

  committedNov 14, 2020
  c1e10ec

• Merge branch 'Add-XBAR' into 3-stage-AXI

  

  Bohan Hu

  committedNov 14, 2020
  dbe7915

• 3 stage pipeline, pass xv6, rtt

  

  Bohan Hu

  committedNov 14, 2020
  0583532

Commits on Nov 13, 2020

• TLB test passed

  

  Bohan Hu

  committedNov 13, 2020
  9b0d0ae

• Add hazard detection

  

  Bohan Hu

  committedNov 13, 2020
  21ab24c

• Add tlb

  

  Bohan Hu

  committedNov 13, 2020
  85bc202

Commits on Nov 10, 2020

• pass AXI Tests

  

  Bohan Hu

  committedNov 10, 2020
  541548d

Commits on Nov 7, 2020

• Merge branch '4-stage-pipeline' into Add-XBAR

  

  Bohan Hu

  committedNov 7, 2020
  ae07753

• fixed exception on SRET

  

  Bohan Hu

  committedNov 7, 2020
  150e638

Commits on Nov 5, 2020

• fixed s status interrupt

  

  Bohan Hu

  committedNov 5, 2020
  7166a2e

Commits on Nov 3, 2020

• Add crossbar

  

  Bohan Hu

  committedNov 3, 2020
  3acd839

Commits on Nov 2, 2020

• fixed MRPV bug (critical)

  

  Bohan Hu

  committedNov 2, 2020
  0a8da12

• Mark tVal as a bug

  

  Bohan Hu

  committedNov 2, 2020
  47e2467

• Check priviledge in decode stage

  

  Bohan Hu

  committedNov 2, 2020
  a95d4c5

Commits on Nov 1, 2020

• Stuck on booting linux

  

  Bohan Hu

  committedNov 1, 2020
  a51edf9

Commits on Oct 31, 2020

• Boot xv6

  

  Bohan Hu

  committedOct 31, 2020
  6f8c7a3

Commits on Oct 30, 2020

• Stupid CSR bug

  

  Bohan Hu

  committedOct 30, 2020
  3aa1688

• Emit A/D logic to pass the test

  

  Bohan Hu

  committedOct 30, 2020
  cbfef3a

• todo: PTW access-modify A D bit should be added

  

  Bohan Hu

  committedOct 30, 2020
  6309229

Commits on Oct 29, 2020

• Passed P tests

  

  Bohan Hu

  committedOct 29, 2020
  df41bc2

Commits on Oct 26, 2020

• Add PTW to Mem, can throw page fault now

  

  Bohan Hu

  committedOct 26, 2020
  cb06a9c

• Connect LSU

  

  Bohan Hu

  committedOct 26, 2020
  48ec014

Commits on Oct 25, 2020

• Connect the MMU with PTW

  

  Bohan Hu

  committedOct 25, 2020
  0656b75

Commits on Oct 24, 2020

• Added 'A' Support

  

  Bohan Hu

  committedOct 24, 2020
  0f53ca4

• All test passed

  

  Bohan Hu

  committedOct 24, 2020
  091ae64

• Integrate the mem unit into exu

  

  Bohan Hu

  committedOct 24, 2020
  287f414

• Checkpoint: Can run rtt

  

  Bohan Hu

  committedOct 24, 2020
  edacc84

Commits on Oct 21, 2020

• fixed timer interrupt

  

  Bohan Hu

  committedOct 21, 2020
  ab22751

• Boot RT-Thread

  

  Bohan Hu

  committedOct 21, 2020
  dd51ba6

Commits on Oct 20, 2020

• connect clint to csr

  

  Bohan Hu

  committedOct 20, 2020
  158dad0

• Add clint, the exception info transfer btw stages

  

  Bohan Hu

  committedOct 20, 2020
  0fb823c

• partly finished axi interface

  

  Bohan Hu

  committedOct 20, 2020
  de6b8d5

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