Skip to content

Issues: chipsalliance/verible

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

451 Open 478 Closed
451 Open 478 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

how compile verible on windows？ formatter Verilog code formatter issues
#1974 opened Jul 21, 2023 by durongze
4
Symbol table is missing a lot of references
#1961 opened Jul 10, 2023 by ivan444
@glatosinski
1
feature request: example code for using python boost with verible-verilog-syntax
#1957 opened Jul 9, 2023 by kbroch-rivosinc
Formatting a long initialization of a structure formatter Verilog code formatter issues
#1953 opened Jul 5, 2023 by JanOlencki
how to parser a file with macro？ rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1952 opened Jul 3, 2023 by ddppt-yy
2
verible_verilog_syntax.py: CRLF in Windows causes JSON start/end values to not match file read in as bytes rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1950 opened Jun 16, 2023 by craigc40
1
Project tool: crash on some caliptra-rtl files bug Something isn't working language-server Language server related issues project-tool Issues related to the project tool/symbol table
#1946 opened Jun 13, 2023 by hzeller
@glatosinski
6
Function Argument Alignment/Preserve formatter Verilog code formatter issues
#1943 opened Jun 7, 2023 by jkshah
System Verilog If-else if constraint formationg formatter Verilog code formatter issues
#1942 opened Jun 6, 2023 by jkshah
Event triggering not recognised as valid syntax bug Something isn't working rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1940 opened Jun 5, 2023 by matlupi
5
How to align if else block in case statement? bug Something isn't working formatter Verilog code formatter issues
#1935 opened May 24, 2023 by 3verness
Rule for undeclared variable enhancement New feature or request style-linter Verilog style-linter issues
#1929 opened May 21, 2023 by hrivu21
1
arm64/centos7 fails to build
#1926 opened May 17, 2023 by hzeller
@AdamOlech
6
Change tagging to not include hash ? e.g. v0.0-3255-gfe86b47d -> v0.0.3255
#1923 opened May 16, 2023 by hzeller
2
Provide a public API for the formatter
#1921 opened May 16, 2023 by 17Reset
2
Building from Python
#1919 opened May 15, 2023 by 17Reset
3
Crash on macro chain bug Something isn't working formatter Verilog code formatter issues preprocessor anything related to preprocessing (conditionals, macros, etc.)
#1915 opened May 11, 2023 by jjts
linter: Add lint rule for DFF name suffixes enhancement New feature or request style-linter Verilog style-linter issues
#1913 opened May 10, 2023 by sifferman
@IEncinas10
5
ReadTheDocs CI throws ImportError with urllib documentation Improvements or additions to documentation
#1910 opened May 5, 2023 by jbylicki
@AdamOlech
5
Autoc-ompletion feature request language-server Language server related issues
#1905 opened May 3, 2023 by adibis
2
Auto-push to chipsalliance/homebrew-verible from CI package management General support for external package managers
#1904 opened May 2, 2023 by hzeller
@tgorochowik
2
Release doesn't contain binaries for MacOS
#1897 opened Apr 28, 2023 by eszpotanski
1
syntax error at token "`elsif" formatter Verilog code formatter issues
#1893 opened Apr 26, 2023 by skazarynau1
@tgorochowik
3
different formatting of return and non-return functions bug Something isn't working formatter Verilog code formatter issues
#1892 opened Apr 25, 2023 by skazarynau1
formatting failed to converge bug Something isn't working formatter Verilog code formatter issues
#1891 opened Apr 25, 2023 by skazarynau1
@jbylicki
ProTip! Mix and match filters to narrow down what you’re looking for.