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451 Open 478 Closed
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Issues list

Indicate path when using find/find_all.
#1890 opened Apr 25, 2023 by futurehome
Instantiations Wrapped with One Port formatter Verilog code formatter issues
#1889 opened Apr 24, 2023 by bkueffle
1
@jbylicki
2
verible-verilog-format fails verification with macro formatter Verilog code formatter issues
#1883 opened Apr 22, 2023 by nathanbeckmann
@jbylicki
5
Use colored patch output in diff ?
#1874 opened Apr 19, 2023 by hzeller
@IEncinas10
6
Use tabs for indentation instead of spaces enhancement New feature or request formatter Verilog code formatter issues
#1859 opened Apr 9, 2023 by hrivu21
1
Build fails needs the c++20 flag build system matters pertaining to building Verible
#1856 opened Apr 5, 2023 by yurivict
11
Bracket position depends on comment length formatter Verilog code formatter issues
#1855 opened Apr 4, 2023 by skazarynau1
2
format long for with commas formatter Verilog code formatter issues
#1854 opened Apr 4, 2023 by skazarynau1
alignment by equals sign (feature req) formatter Verilog code formatter issues
#1853 opened Apr 4, 2023 by skazarynau1
No indent on a new line in a function call with macro formatter Verilog code formatter issues
#1852 opened Apr 4, 2023 by skazarynau1
[Discussion] Smoke Test improvement roadmap help wanted Extra attention is needed
#1839 opened Mar 28, 2023 by jbylicki
1
Sequence rejects clocking event as invalid syntax rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1838 opened Mar 28, 2023 by jbylicki
Macro call inside preprocessor control flow causes syntax erros rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1837 opened Mar 28, 2023 by jbylicki
Cannot go to module instantiation definition when file is located in different path language-server Language server related issues
#1834 opened Mar 24, 2023 by miguelcruz97
Option to have alignment only apply to blocks of code formatter Verilog code formatter issues
#1832 opened Mar 24, 2023 by patrickrst
1
linter: Add rule for spaces around binary operators enhancement New feature or request style-linter Verilog style-linter issues
#1829 opened Mar 23, 2023 by glatosinski
linter: Add rule for allowing ASCII characters enhancement New feature or request style-linter Verilog style-linter issues
#1828 opened Mar 23, 2023 by glatosinski
linter: Add rule for file header comment enhancement New feature or request style-linter Verilog style-linter issues
#1827 opened Mar 23, 2023 by glatosinski
linter: Add rule for spaces around keywords enhancement New feature or request style-linter Verilog style-linter issues
#1826 opened Mar 23, 2023 by glatosinski
linter: Add rule for indented sections enhancement New feature or request style-linter Verilog style-linter issues
#1825 opened Mar 23, 2023 by glatosinski
Semicolon, comma and parenthesis alignment issues formatter Verilog code formatter issues
#1812 opened Mar 15, 2023 by Lcr20010506
2
Preprocessor cannot recognize nested define
#1796 opened Mar 11, 2023 by LoveMyPillow
SVA: syntax error around fail-action block under ifdef formatter Verilog code formatter issues
#1792 opened Mar 9, 2023 by svenka3
1
How to format task and functions parameters the same as ansi module ports? formatter Verilog code formatter issues
#1770 opened Mar 6, 2023 by prokie
1
Verible JSON configuration enhancement New feature or request style-linter Verilog style-linter issues
#1742 opened Feb 23, 2023 by qarlosalberto
ProTip! Adding no:label will show everything without a label.